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1 semiconductor [ /title (HMP9701A) /subject (ac97 audio codec) /author () /keywords (harris semiconductor, audio codecs, pc audio, pc98, pc98, pc 98, pc99, pc 99, pc99, thd, pci audio, ac97, ac97, ac 97, ac98, ac 98, ac98, snr, ac link, pc97, pc 97, pc97, gam pci sound, total harmonic distortion, signal to noise ratio, record gain ) /creator () /docinfo pdfmark [ /pagemode /useoutlines /docview pdfmark november 1998 HMP9701A ac97 audio codec features ? compliant with the audio codec 97 standard ? high fidelity 16-bit sd converters - dac snr 87db - adc snr 85db ? additional a/d for microphone pass-through ? ac link serial interface compatible with ac97 digital controllers ? fixed 48khz sampling rate ? 6 channel input mixer ? programmable powerdown modes ? 48 lead tqfp package ? single +5v supply applications ? multimedia pc applications - desk top pcs - notebook pcs - pci sound cards - motherboards ? video conferencing ? speaker phones table of contents page functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 serial digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 control register description . . . . . . . . . . . . . . . . . . . . . . . . 8 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ac and dc electrical speci?cations . . . . . . . . . . . . . . . . . 13 adc/dac filter response curves . . . . . . . . . . . . . . . . . . 17 ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 description the HMP9701A is the next generation pc based audio codec solution. the HMP9701A is compliant to the new ac97 stan- dard and, as such, interfaces to any ac97 compliant digital controller. the HMP9701A offers the designer a solution to sat- isfy the demand for ?exibility and improved high fidelity sound in a pc environment. as part of the ac97 pc audio standard architecture, the HMP9701A helps pave the way for pc97 compliant desktop, portable and entertainment pcs with a cost effective high-quality audio solution. as the analog front end of the ac97 chipset, the HMP9701A accepts line level audio inputs from seven different sources and converts the analog audio to 16-bit digital streams of either ste- reo or mono data. the 48 kss data is transmitted to the control- ler via the ac97 standard ?ve wire interface. the controller sends digital audio data to the HMP9701A to be converted to analog stereo or monaural line output using two dacs. we include an additional adc to be used for acoustic echo canceling needed for video conferencing applications. this adc has a dedicated microphone input. it has the same high quality performance as the stereo adcs. the small 48 lead tqfp (thin 1.5mm and 7mm x 7mm footprint quad flat pack- age) makes it easy to locate the analog codec close to the ana- log sources. thus, reducing noise and lowering the cost of implementation. ordering information part number temp. range ( o c) package pkg. no. HMP9701Acn 0 to 70 48 ld tqfp ? q48.7x7a hmp9701eval2 pci bus evaluation board (includes codec) ? tqfp is also known as pqfp and mqfp. caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 file number 4473.1 for a possible substitute product call central applications 1-800-442-7747 or email: centapp@harris.com obsolete pr oduct
2 functional block diagram functional description the HMP9701A is a full-duplex stereo audio codec compliant to the ac97 codec speci?cation. this component is designed for use in multimedia and business personal computers. the codec includes full duplex stereo converters, a mic pass through adc, complete on-chip anti-alias ?ltering, and a 5 channel analog mixer with programmable gain and attenuation. analog inputs the HMP9701A has 4 stereo inputs (line_in, cd, video, and aux), two microphone level inputs (mic1 and mic2), and one mono line level input (phone). a multiplexer is provided to independently select the right and left record sources from the analog inputs listed above. in addition, the output stereo mix (line_out) or its mono equivalent may also be selected as a record source. a gain block is available to amplify the mic inputs by 20db to compensate for the difference between line levels and typical condenser microphone levels. besides being fed to the record select mux, all analog inputs can be mixed (see analog mixer) with the stereo out- put from the playback dacs. note: all analog inputs except phone and pc_beep can be output on mono_out. there is a dedicated analog input, pc_beep, for the standard beep signal provided on most pc/compatible computers for power on self test and boot audio status indication. this input is mixed into each channel of the stereo line outputs. record adcs the HMP9701A provides 3 sd adcs to record one dedi- cated microphone input and 2 user selectable analog inputs. the user selectable analog inputs are routed to the stereo adcs via an programmable input multiplexer. the multi- plexer is programmed to select the 2 record channels via the record select register (1ah). each of the record channels pass through a programmable gain block before each adc. the record gain for each chan- nel is set individually and ranges from 0db to 22.5db in 1.5db increments (see record gain registers 1ch and 1eh). the gain block can also be used to mute each chan- nel. note: an additional gain block provides 20db of gain on the mic channel if activated (see mic volume register 0eh). the HMP9701A uses oversampling sd adcs which only require a single pole passive ?lter for anti-alias ?ltering. the ?lter for the left, right and mic channels is realized by placing a 1nf capacitor between the afilt1, afilt2, and afilt3 pins and analog ground respectively. playback dacs the HMP9701A uses oversampling single bit sd dacs to convert the stereo playback sample to an analog line level output. the output of the dacs pass through internal recon- struction ?lters that do not require any external components. gain 0db/20db mono vol sd d/a ac link interface sd d/a mic1 mic2 line_in cd video aux pc_beep mono_out line_out sync bit_clk sdata_out sdata_in reset phone g a m g a m g a m g a m g a m g a m gam gam ac97 control/configuration (64 registers) HMP9701A ac97 audio codec stereo signal path mono signal path record gain master vol sd a/d sd a/d sd a/d ? ? ? ? mic sel mono sel record select HMP9701A
3 analog mixer the analog mixer generates two outputs, one stereo and one mono. the stereo output is used to drive line_out and is composed of a stereo mix of all analog input sources and the audio output from the dacs. the mono output drives mono_out, and it is user selectable as either mic only or a mono mix of all the analog and pcm sources except the phone and pc_beep inputs. the inputs to the analog mixer pass through gain/attenu- ate/mute (gam) blocks. each gain block provides volume control from -34.5db to +12db in 1.5db increments (see input volume registers 0ch - 18h). additionally, the gam blocks can be used to mute individual mixer inputs. an addi- tional gain of 20db is provided for the selected mic input. note: for best snr performance, the gam block for the dac output should be used to control pcm analog volume rather than digitally attenuating the dac pcm input to take advan- tage of full resolution conversions. clocking the HMP9701A derives its internal clock from an externally attached 24.576mhz crystal. the crystal and 2 capacitors are attached to the xtl_in and xtl_out pins, and it should be fundamental-mode/parallel resonant with a load capacitor as speci?ed by the crystal manufacturer (typically 12-30pf). for an example circuit, refer to the typical appli- cation schematic. an external cmos clock may be connected to xtl_in instead of a crystal. if this external clocking option is used, xtl_out should be left ?oating. please note: no capaci- tors are used on the crystal pins in this mode. the HMP9701A divides the clock source by 2 to derive the bit_clk provided to the companion digital controller. the digital controller should divide the provided bit_clk by 256 to generate the 48khz sync signal used to de?ne the audio frame transmitted over the serial digital interface (see serial digital interface section) serial digital interface audio data format the HMP9701A supports 16-bit 2s complement linear pcm data for record and playback. the 16-bit 2s complement for- mat (also called 16-bit signed format) is the standard method of representing 16-bit digital audio. this format gives 96db theoretical dynamic range and is the standard for compact disk audio players. this format uses the value -32768 (8000h) to represent minimum analog amplitude while 32767 (7fffh) represents maximum analog amplitude. digital serial interface (ac link) the HMP9701A is linked to an ac97 digital controller via a 5 pin digital serial interface as shown in figure 1. this inter- face, the ac-link, supports bidirectional, ?xed rate, serial data streams. the data transfers are based on a time divi- sion multiplexed (tdm) protocol that provides for multiple input and output audio streams together with control and sta- tus data. the ac-link protocol is based on incoming and out- going audio frames which are each divided into 12 data slots as shown in figure 2. the HMP9701A allocates data slots for 2 pcm playback channels, 2 pcm record channels, codec control, codec status, and a pcm microphone record channel. the remaining unused time slots are reserved. sync bit_clk sdata_out sdata_in reset HMP9701A ac97 audio codec figure 1. HMP9701A connection to ac97 controller ac97 digital controller pcm left rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd mic rsrvd pcm right status data tag status addr incoming audio streams pcm left rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd pcm right cmd data tag cmd addr outgoing audio streams sync slot no. 0123456789101112 tag phase data phase figure 2. ac link bidirectional data frame HMP9701A
4 the HMP9701A generates a serial bit clock (bit_clk) at 12.288mhz for synchronous data transfers on the ac link. data is output on sdata_in by the rising edge of bit_clk, and serial data is sampled on sdata_out by the falling edge of bit_clk. an audio frame transfer is initiated by the assertion of sync for the 16 bit_clks comprising the tag phase of the audio frame. the sync signal must be asserted at a ?xed 48khz rate, and it can be derived by dividing down the bit_clk. the tag phase is a 16-bit data slot (slot 0) wherein each bit is a data valid ?ag for an associated time slot within the cur- rent audio frame. a 1 in a given bit position of slot 0 indi- cates that the corresponding time slot within the audio frame contains valid data. if the HMP9701A tags a slot invalid, it will set the data bits comprising that slot to zero. ac link output frame (sdata_out) the audio output frame contains data targeted for the HMP9701As dac inputs, and control registers. this data is transmitted in slots 1 through 4 of the audio frame as shown in figure 2. the tag slot, slot 0, is a special reserved time slot containing 16 bits that tell the ac-link interface circuitry the validity of the following data slots. the HMP9701A is synchronized to the beginning of a new audio output frame when sync makes a low to high transi- tion and is sampled low by the falling edge of bit_clk as shown in figure 3. on the next rising of bit_clk, the ac97 controller drives sdata_out with the ?rst bit of slot 0 (valid frame bit) which is then sampled by the HMP9701A on the subsequent falling edge of bclk. the controller drives the remaining audio frame bits out on sdata_out with each rising edge of bclk, and the HMP9701A samples these bits on the subsequent falling edge. the ?rst bit of the output audio frame (slot 0, bit 15) ?ags the validity of the entire audio frame. if the valid frame bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. the HMP9701A moni- tors the next 4-bit positions to determine whether the data in the control and pcm output data slots is valid. the remaining 8 bits in slot 0 are ignored as they are associ- ated with reserved data slots. the 20-bit data word in each time slot must be transmitted msb ?rst. if the data word targeted for a time slot is less than 20 bits, the data word must be msb justi?ed in the most signi?cant bits of the time slot with the unused bits set to zero. for example, an 8-bit audio sample would be transmitted in bits 19-12 of the time slot with the trailing 12 bits set to zero. the msb of the audio sample would map to bit 19 of the time slot. note: for the playback of mono audio streams, the digital controller must send the same sample to each pcm output channel. audio output slot 1: control address the bits in slot 1 are used to access the 16-bit control/status registers within the HMP9701A. the address space allo- cated in slot 1 allows up to 64 sixteen bit registers, however, only the even registers are valid (see control/status register section for a complete register map). the control registers are read/writable to provide more robust testability. a read or write command is initiated by setting the read/write bit (bit 19) in slot 1. a complete bit map for slot 1 is given in the table 1. note: control data will only be loaded into the target registers if slot 2 (control data) is ?agged as being valid. valid frame slot slot slot 0 0 0 bit 19 bit 0 bit 19 bit 0 bit 19 bit 0 sync sdata_out bit_clk 12.288mhz 81.4ns tag phase data phase 20.8 m s (48khz) time slot valid bits (1 = time slot contains valid data) 1 = frame contains valid data slot 1 slot 2 slot 12 figure 3. ac link audio output frame 12 2 1 valid frame slot 1 slot 2 sdata_out bit_clk previous audio frame HMP9701A samples sync assertion HMP9701A samples first bit of audio output sync figure 4. start of audio output frame HMP9701A
5 audio output slot 2: control data this slot is used to deliver the 16-bit control data if the cur- rent control register access is a write operation (bit 19 of slot 1 is set to 0). the bit map for slot 2 is given in table 2. audio output slot 3: pcm playback left channel this time slot contains the audio sample that will be input to the left channel dac. the HMP9701A dac resolution is 17 bits. all audio samples of 17 or less bits should be msb jus- ti?ed within the 20-bit frame, and the trailing bits should be set to 0. audio samples greater than 17 bits will be rounded to 17 bits. audio output slot 4: pcm playback right channel this time slot contains the audio sample that will be input to the right channel dac. the dacs resolution is 17 bits. all audio samples of 17 or less bits should be msb justi?ed within the 20-bit frame, and the trailing bits should be set to 0. audio samples greater than 17 bits will be rounded to 17 bits. audio output slots 5-12: reserved audio output slots 5-12 are reserved for future use and should be set to 0 for proper operation. ac link input frame (sdata_in) the audio input frame contains captured audio samples and codec status for output onto the ac-link. the codec status is transmitted in slots 1 and 2, and the 16-bit captured audio samples are returned in slots 3, 4 and 6 as shown in figure 2. as before, the tag slot, slot 0, is a special reserved time slot containing 16 bits that tell the ac-link interface cir- cuitry the validity of the following data slots. the HMP9701A starts a new audio input frame when sync makes a low to high transition and is sampled low by the falling edge of bit_clk as shown in figures 5 and 6. on the next ris- ing edge of bit_clk, the HMP9701A drives sdata_in with the ?rst bit of slot 0 (codec ready bit). the HMP9701A drives the remaining audio frame bits out on sdata_in with each ris- ing edge of bit_clk. note: sync must be synchronous to bit_clk. the ?rst bit of an input audio frame (slot 0, bit 15) indicates whether the hmp970s ac link is functional. if the codec ready bit is a 0, the HMP9701A is not ready for normal operation. if the codec ready bit is 1, the HMP9701A is ready to perform control and status register transfers. at this point, it is the responsibility of the digital controller to exam- ine the powerdown control/status register (see control reg- ister section) to determine the operational state of the codec subsections. the 12 bits following the codec ready bit in slot 0 identify which of the 12 time slots contain valid data. the HMP9701A outputs each time slots data word msb ?rst on sdata_in. all non-valid bit positions (for active or inac- tive time slots) are stuffed with 0s by the HMP9701A. input audio slot 1: status address this slot echoes the index of the control register whose con- tents are returned in slot 2. the data in this register is the result of a control register read operation initiated by an out- put audio frame transfer. table 1. bit map for slot 1: control address bits description comment 19 read/write 1 = read, 0 = write 18:12 control register index identifies the target control register 11:0 reserved set to 0 table 2. bit map for slot 2: control data bits description comment 19:4 control register write data set to 0 if read operation 3:0 reserved set to 0 table 3. bit map for slot 3: pcm playback left channel bits description comment 19:0 pcm audio sample for left channel set unused bit positions to 0 table 4. bit map for slot 4: pcm playback right channel bits description comment 19:0 pcm audio sample for right channel set unused bit positions to 0 table 5. bit map for slot 1: status address bits description comment 19 reserved stuffed with 0 18:12 control register index echo of control register index for which data is being returned 11:0 reserved stuffed with 0s codec ready slot 1 slot 2 sdata_in bit_clk previous audio frame HMP9701A samples sync assertion HMP9701A outputs first bit of audio input frame sync figure 5. start of audio input frame HMP9701A
6 input audio slot 2: status data this slot delivers control register read data. input audio slot 3: pcm record left channel this slot contains an audio sample captured by the left chan- nel adc. the resolution of the adc is 16 bits and is msb justi?ed in the 20-bit slot. input audio slot 4: pcm record right channel this slot contains an audio sample captured by the right channel adc. the resolution of the adc is 16 bits and is msb justi?ed in the 20-bit slot. input audio slot 6: microphone record channel this slot contains an audio sample captured by the dedi- cated microphone adc. the resolution of the adc is 16 bits and is msb justi?ed in the 20-bit slot. this input allows higher performance echo cancellation algorithms in speaker phone applications. slots 5, 7-12: reserved audio input slots 5, and 7-12 are reserved, and they are set to 0. low power modes the HMP9701A may be put in a programmable powerdown state to reduce power when no activity is required. the state of powerdown is controlled by the powerdown register (26h). this register provides 6 commands to powerdown various sec- tions of the HMP9701A. a summary of the power down com- mands is given in table 10 with a more complete description given in the control register section. note, the HMP9701A is a fully static design which will preserve the contents of the inter- nal control registers if the internal clock is stopped. table 6. bit map for slot 1: status data bits description comment 19:4 control register read data stuffed with 0s if slot tagged invalid 3:0 reserved stuffed with 0s table 7. bit map for slot 3: left channel record data bits description comment 19:4 pcm record sample left channel 16-bit audio sample from left record adc 3:0 reserved stuffed with 0s table 8. bit map for slot 4: right channel record data bits description comment 19:4 pcm record sample right channel 16-bit audio sample from right record adc 3:0 reserved stuffed with 0s figure 6. ac link audio input frame codec ready slot slot slot 0 0 0 bit 19 bit 0 bit 19 bit 0 bit 19 bit 0 sync sdata_in bit_clk 12.288mhz 81.4ns tag phase data phase 20.8 m s (48khz) time slot valid bits (1 = time slot contains valid data) 1 = ac link interface is functional slot 1 slot 2 slot 12 12 2 1 table 9. bit map for slot 6: microphone record data bits description comment 19:4 pcm record sample microphone channel 16-bit audio sample from dedicated microphone adc 3:0 reserved stuffed with 0s table 10. summary of powerdown register (26h) bit function pr0 input mux and adc powerdown pr1 dac powerdown pr2 analog mixer powerdown (v ref on) pr3 analog mixer powerdown (v ref off) pr4 digital interface (ac-link) powerdown (external clk off) pr5 internal clk disable HMP9701A
7 ac link powerdown the ac-link interface can be placed in a low power mode by setting pr4 = 1 in the powerdown register (see above). in this mode, both bit_clk and sdata_in are forced to a logic low voltage level. as shown in figure 7 bit_clk and sdata_in are driven low immediately following the decode of the write to the pow- erdown control/status register (26h) with pr4 = 1. once HMP9701A has been instructed to powerdown the ac link, a special wake up sequence is required to return the ac- link to active mode. note: any valid slots of audio output samples in the frame containing the ac link powerdown command will be dropped. waking up the ac-link there are 2 methods for bringing the HMP9701As ac-link out of powerdown mode. the ?rst is a warm reset that preserves reactivates the ac link while preserving the contents of the HMP9701A control registers. the second is a cold reset that reactivates the digital interface while resetting the control registers to their default values. once the ac link has been powered up, its operational readiness will be indicated via the codec ready bit in the audio input frame (slot 0, bit 15). warm ac link reset a warm reset will reactivate the HMP9701As ac-link without altering the current control register values. a warm reset is generated by driving sync high for a minimum of 1 m s in the absence of bit_clk. within normal audio frames sync is a synchronous bit_clk. however, in the absence of bit_clk, sync functions as an asynchronous input that is used to gen- erate a warm reset. the activation of bit_clk will not occur until after the falling edge (high to low transition) of the wake up sync. note: the HMP9701A will not respond to a warm reset via the sync input for 4 audio frame times following the frame that triggered the powerdown. cold ac link reset a cold reset is achieved by asserting reset for a minimum of 1 m s. by driving reset low, bit_clk will be activated, the ac-link will return to normal operation, and all HMP9701A control registers will be initialized to their default values. reset is an asynchronous HMP9701A input. note: the HMP9701A will remain in the reset state as long as reset is asserted low. suggested powerdown sequences figure 8 illustrates the complete powerdown of the HMP9701A. starting from normal operation, sequential writes to the powerdown register are performed to power- down one codec section at a time. after powering down the converters and the analog front end, a ?nal write to pr4 is executed to shut down the HMP9701As digital interface (ac-link). the part will remain in sleep mode with all its reg- isters holding their static values. a warm reset can be used to wake up the ac link which can then be used to sequentially power up each codec section. each section should be powered up sequentially, and the powerdown control/status register (26h) should be read to verify that a powered up section is stable/ready before pre- ceding to power up the next section as shown in figures 8 and 9. note: after a complete powerdown, care must be taken to make sure the analog mixer (pr2, pr3) is powered up and stable before preceding to power up the adcs and dacs. the figure 9 illustrates an HMP9701A powerdown sequence that will keep all the mixers operational with the static volume settings contained in their associated registers. this powerdown scenario could be used to place the HMP9701A in low power mode while preserving the capabil- ity to play a cd (or external line_in source) through the HMP9701A to the speakers. slot 12 previous frame tag write to 26h data pr4 = 1 slot 12 tag sync bclk sdata_out sdata_in note: bclk not to scale. figure 7. ac-link powerdown timing normal adcs analog ac link power off pr0 dacs off pr1 off pr2 or pr3 off pr4 down pr0=1 pr1=1 pr2=1 pr4=1 warm reset pr2=0 and anl=1 pr1=0 and dac=1 pr0=0 and adc=1 default cold reset codec ready =1 figure 8. example of sequential powerdown normal adcs ac link power off pr0 dacs off pr1 off pr4 down pr0=1 pr1=1 pr4=1 warm reset pr1=0 and dac=1 pr0=0 and adc=1 figure 9. HMP9701A powerdown/up with analog alive HMP9701A
8 testability the HMP9701A provides a test mode to support the in cir- cuit test capabilities provided by automatic test equipment (ate). in this mode, the HMP9701A drives its digital ac-link outputs (bit_clk and sdata_in) to a high impedance state. this allows for in circuit testing of the digital controller component of the sound subsystem. the HMP9701A enters ate test mode when sdata_out is sampled high by the trailing edge of reset (see ac timing diagrams). the HMP9701A will remain in test mode until a cold reset returns the part to normal operation. control/status registers the HMP9701A contains a bank of 16-bit control/status reg- isters to control and monitor part operation. the control reg- isters are accessed via the even addresses within the 6-bit address space provided in slot 1 of the audio output frame. the control/status register address map is given in table 20. reset register (index 00h) writing any value to this register performs a register reset that causes all registers to revert to their default values. reading this register returns the ac97 id code that speci?es the optional ac97 features supported by the HMP9701A. this register will read back 0001h to indicate that the HMP9701A provides the optional adc for a dedicated mic channel. master volume control registers (index 02h, 06h) these registers manage the output audio volumes. register 02h sets the master stereo volume (line_out_l, line_out_r) and register 06h controls the mono volume (mono_out). each volume step corresponds to 1.5db. the msb of both registers is the mute bit. when this bit is set to 1 the level for that channel is set at - db. the HMP9701A supports 5 bits of gain control for the stereo line out and mono out. the right and left stereo channels are controlled via mr4:0 and ml4:0 respectively. the mono out- put is controlled by mm4:0. writing a 1 to mr5, ml5, or mm5 will force the volume level to max attenuation, mx4:0 = 11111 (46.5db attenuation). note: if these registers are writ- ten with mx5:0 = 1xxxx, they will read back mx5:0 = 01111. pc beep register (index 0ah) this register controls the level of the pc beep input. the pc beep is attenuated as speci?ed by the contents of this regis- ter and mixed equally into both the right and left output chan- nels. the pc_beep input is attenuated in 3db steps from 0db to 45db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. input volume control (index 0ch- 18h) these registers control the input gain/attenuate/mute (gam) blocks through which each of the analog mixers inputs pass. each gam block has a 5-bit control that supports setting the gain in increments of 1.5db. a total gain range from +12db to -34.5db is supported. the msb of each register is a mute bit that will set the gain to - db when programmed to 1. note: reg- ister 0eh (mic volume register) has an extra bit that is for a 20db boost. when bit 6 is set to 1 the 20db boost is on. record select (index 1ah) this register is used to select the record source for the left and right record adcs. the selections are summarized below in table 14 and 15. table 11. master volume settings mute mx5...mx0 function 0 00 0000 0db attenuation 0 01 1111 46.5db attenuation 0 1x xxxx 46.5db attenuation 1 xx xxxx - db attenuation default value: 8000h (0db gain with mute on) table 12. pc_beep attenuation settings mute pv3:0 function 0 0000 0db attenuation 0 1111 45db attenuation 1 xxxx - db attenuation default value: 8000h (0db gain w/ mute on) table 13. analog mixer input gain settings mute pv3:0 function 0 00000 +12db gain 0 01000 0db gain 0 11111 -34.5db gain 1 xxxx - db gain default: all gam blocks set to mute with 0db gain (see table 20) table 14. record select right channel sr2:0 right record source 0 mic 1 cd_r 2 video_r 3 aux_r 4 line_in_r 5 stereo mix right 6 mono mix 7 phone default: 000 (mic in) HMP9701A
9 record gain registers (index 1ch and 1eh) these registers control the record gain for both the mic input and the selected stereo inputs (see record select register). the gain is programmed in steps of 1.5db and ranges from 0db to +22.5db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel(s) is set at - db. general purpose register (index 20h) this register is used to control several miscellaneous func- tions within the HMP9701A. these include the selection of mic input source, the selection of mono_out source, and activation of adc/dac loopback mode. when loopback mode is enabled, the adc output is looped back to the dac input bypassing the ac-link, thus allowing for full system per- formance measurements. powerdown control/status register (index 26h) this register is used to program the HMP9701As power- down states and monitor subsystem status. the upper bits of this register are used to power up/down individual sec- tions within the codec as summarized in table 18. the lower byte of this register is used to monitor the status of individual sections with in the HMP9701A. the status bits, as summarized in table 19, indicate whether a subsection is in its normal operational state (ready). note: the status bits are read only, and writes to this register will have no effect on the state of these bits. when the ac-link codec ready indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac97 control and status registers are in a fully operational state. it is the responsibility of the digital controller to further probe the powerdown control/status register to determine exactly which subsections, if any, are ready. reserved registers (index 28h - 7ah) these are reserved. do not write to these registers. vendor id registers (index 7ch - 7eh) this register contains the harris semiconductor vendor id. the id method is a microsofts plug and play vendor id code with f7:0 the ?rst character of that id, s7:0 the second character and t7:0 the third character. these three charac- ters are ascii encoded, and they will read back as hrs. the rev7:0 ?eld is for the revision number. table 15. record select left channel sl2:0 right record source 0 mic 1 cd_l 2 video_l 3 aux_l 4 line_in_l 5 stereo mix right 6 mono mix 7 phone default: 000 (mic in) table 16. record gain settings mute pv3:0 function 0 0 1111 +22.5db gain 0 0 0000 0db gain 1 x xxxx - db gain default: 8000h (0db gain with mute on) table 17. general purpose control bit function mix mono output select (0 = mix, 1 = mic) ms mic select (1 = mic2, 0 = mic1) lpbk adc/dac loopback mode default: 0000h table 18. powerdown control bit function pr0 input mux and adcs (1 = pwr down, 0 = pwr up) pr1 dacs (1 = pwr down, 0 = pwr up) pr2 analog mixer powerdown with v ref left on (1 = pwr down, 0 = pwr up) pr3 analog mixer powerdown with v ref turned off (1 = pwr down, 0 = pwr up) pr4 digital interface (ac link) powerdown (bclk off) (1 = pwr down, 0 = pwr up) pr5 internal clock disable (1 = clk off, 0 = clk on) default: na table 19. powerdown status bit function ref v refs at nominal level (1 = v ref ready, 0 = v ref down) anl analog mixer powerdown (1 = mixer up, 0 = mixer down) dac dac ready for audio samples (1 = ready, 0 = not ready) adc adc section ready to record (1 = ready, 0 = not ready) default: na HMP9701A
10 table 20. control/status register address map reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x 0 0 0 0 0 0 0 00000001 na 02h master volume mute x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h reserved x x x x x x x x x x x x x x x x x 06h master volume mono mute x x x x x x x x x mm5 mm4 mm3 mm2 mm1 mm0 8000h 08h reserved x x x x x x x x x x x x x x x x x 0ah pc_beep volume mute x x x x x x x x x x pv3 pv2 pv2 pv0 x 8000h 0ch phone volume mute x x x x x x x x x gn5 gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute x x x x x x x x 20db gn5 gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out vol mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 1ah record select x x x x x sl2 sl1 sl0 x x x x x sr2 sr1 sr0 0000h 1ch record gain mute x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 8000h 1eh record gain mic mute x x x x x x x x x x x gm3 gm2 gm1 gm0 8000h 20h general purpose x x x x x x mix ms lpbk x x x x x x x 0000h 22h reserved x x x x x x x x x x x x x x x x x 24h reserved x x x x x x x x x x x x x x x x x 26h powerdown ctrl/stat x x pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc na 28h reserved x x x x x x x x x x x x x x x x x .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 7ah vendor reserved x x x x x x x x x x x x x x x x x 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4852 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5300 HMP9701A HMP9701A
11 pinout HMP9701A (tqfp) top view line_in_r line_in_l mic2 mic1 cd_r cd_l video_r video_l aux_r aux_l phone cd_gnd line_out_r line_out_l nc reserved nc afilt2 afilt1 v refout v ref agnd v aa afilt3 mono_out v aa reserved nc nc nc nc nc nc nc nc agnd v dd xtl_in xtl_out gnd sdata_out bit_clk gnd sdata_in v dd sync reset pc_beep 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pin descriptions name tqfp pin number input/ output description digital i/o reset 11 i reset - this active low signal causes a HMP9701A hardware reset that will return the control/sta- tus registers to their default conditions. sync 10 i sync - 48khz sync pulse which de?nes the beginning of serial audio i/o frames. note: must be synchronous to bit_clk. bit_clk 6 o bit clock - 12.288mhz serial data clock derived by dividing down 24.576mhz crystal input. sdata_out 5 i serial data out - output bit stream that contains audio playback samples as well as control data. this input is sampled on the falling edge of bit_clk. sdata_in 8 o serial data in - input bit stream that contains recorded audio samples as well as codec status in- formation. data output on the rising edge of bit_clk. analog i/o pc_beep 12 i pc beep. mono input for pc beep pass through to line_out. this input is attenuated from 0db to 45db in 3db steps and then summed with left and right line outputs (line_out_l, line_out_r) phone 13 i phone. mono input from telephony subsystem speaker phone (or dlp - down line phone) mic1 21 i microphone input 1. the mic input may be either line-level or -20db from line-level. in the latter case, a software controlled 20db gain block may be activated. mic2 22 i microphone input 2. the mic input may be either line-level or -20db from line-level. in the latter case, a software controlled 20db gain block may be activated. line_in_l 23 i left line input. the left line-level may be selected for recording via one of the stereo adcs via the input mux. in addition, this input can be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with left line output (line_out_l). HMP9701A
12 line_in_r 24 i right line input. the right line-level may be selected for recording via one of the stereo adcs via the input mux. in addition, this input can be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with right line output (line_out_r). cd_l 18 i left cd audio channel. this line-level input may be input to one of the stereo adcs via the input mux. it can also be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with the left line output (line_out_l). cd_gnd 19 i cd audio analog ground. cd_r 20 i right cd audio channel. this line-level input is selected for input to one of the stereo adcs via the input mux. it can also be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with the right line output (line_out_r). video_l 16 i left video input. this line-level input is driven with the left channel audio track from a video source. the signal is selected for input to one of the stereo adcs via the input mux, and it can be gained/at- tenuated from +12db to -34.5db in 1.5db steps and then summed with left line output (line_out_l). video_r 17 i right video input. this line-level input is driven with the right channel audio track from a video source. the signal is selected for input to one of the stereo adcs via the input mux, and it can be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with right line output (line_out_r). aux_l 14 i left auxiliary input. this line-level input is input to one of the stereo adcs via the input mux. it can also be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with the left line output (line_out_l). aux_r 15 i right auxiliary input. this line-level input is input to one of the stereo adcs via the input mux. it can also be gained/attenuated from +12db to -34.5db in 1.5db steps and then summed with the right line output (line_out_r). line_out_l 35 o left line output. this line level output is the post-mixed output for the left audio channel. the audio out- put passes through a master volume block that provides attenuation from 0db to 45db in 1.5db steps. line_out_r 36 o right line output. this line level output is the post-mixed output for the right audio channel. the audio output passes through a master volume block that provides attenuation from 0db to 45db in 1.5db steps. mono_out 37 o mono output. this user selectable line level output is either the post-mixed output or the micro- phone input. the mono output passes through a mono volume block that provides attenuation from 0db to 45db in 1.5db steps. miscellaneous v ref 27 o voltage reference. nominal 2.25v reference output. should not be used to sink or source current. v refout 28 o voltage reference out. nominal 2.25v reference output with 5ma drive capability. intended a microphone bias. afilt1 29 o anti-alias filter 1 (left record channel). this pin requires a 1nf capacitor to analog ground for proper operation. afilt2 30 o anti-alias filter 2 (right record channel). this pin requires a 1nf capacitor to analog ground for proper operation. afilt3 31 o anti-alias filter 3 (mic record channel). this pin requires a 1nf capacitor to analog ground for proper operation. xtl_in 2 i 24.576mhz crystal input. this pin may also be used to input an external 24.576mhz clock source. xtl_out 3 o 24.576mhz crystal output. leave this pin unconnected when using an external clock source. v aa 25, 38 i analog supply voltage (5.0v). agnd 26, 42 i analog ground. v dd 1, 9 i digital supply voltage (5.0v). gnd 4, 7 i digital ground. reserved 33,39 these pins should not be connected externally to any device. they must be left floating! pin descriptions (continued) name tqfp pin number input/ output description HMP9701A
13 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0v input voltages. . . . . . . . . . . . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions temperature range HMP9701Acn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c thermal resistance (typical, note 1) q ja ( o c/w) tqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dissipation rating assumes device is mounted wit h all leads soldered to printed circuit board. electrical speci?cations v cc = 5.0v, t a = 25 o c, note 1 parameter symbol test condition HMP9701Acn units min typ max power supply characteristics power supply current digital i ccop f clk = 24.576mhz, v dd = 5.0v, outputs not loaded - - 35 ma analog i ccop f clk = 24.576mhz, v aa = 5.0v, outputs not loaded - - 80 ma power supply rejection (1khz, 10mv rms ) - 50 - db digital i/o input logic high voltage digital inputs v ih v dd = max 2.0 - - v xtl_in 0.7 * v dd --v input logic low voltage digital inputs v il v dd = min - - 0.8 v xtl_in - - 0.3 * v dd v input logic current i ih , i il v dd = max input = 0v or 5.25v -10 - +10 m a output logic high voltage v oh i oh = -4ma, v dd = max 2.4 - - v output logic low voltage v ol i ol = 4ma, v dd = min - - 0.4 v three-state output current leakage i oz -10 - +10 m a rise/fall time (sdata_in, bit_clk) t r , t f note 1 - - 6.0 ns input/output capacitance c in clk frequency = 1mhz, note 2, all measurements referenced to ground t a = 25 o c --8pf timing speci?cations (notes 1, 5) parameter symbol test condition HMP9701Acn units min typ max bit_clk frequency 24.576mhz xtal, note 2 - 12.288 - mhz bit_clk period t bcp 24.576mhz xtal, note 2 - 81.4 - ns bit_clk high t bch note 2 32.56 - 48.84 ns bit_clk low t bcl note 2 32.56 - 48.84 ns HMP9701A
14 sync pulse frequency - 48 - khz sync period t sp - 20.8 - m s sync high t sh -16 * t bcp - m s sync low t sl - 240 * t bcp - m s setup time sdata_out, sdata_in, sync to bit_clk t su note 2 15 - - ns hold time sdata_out, sdata_in, sync to bit_clk t hd 5- -ns reset low pulse width (for cold reset) t crl 1.0 - - m s reset inactive to bit_clk start up (for cold reset) t r2bc 2 * t bcp --ns sync active high pulse width (for warm reset) t srh - 1.3 - m s sync inactive low to bit_clk start up (for warm reset) t s2bc 2 * t bcp --ns end of slot 2 to bit_clk, sdata_in low (for ac link powerdown) t pdwn --1 m s sdata_out to reset high (for ate test mode) t su2rst 15 - - ns reset high to hi-z (for ate test mode) t hz note 2 - - 25 ns timing speci?cations (notes 1, 5) (continued) parameter symbol test condition HMP9701Acn units min typ max digital filter characteristics (note 2) parameter min typ max units passband 0 - 0.4xfs hz transition band 0.4xfs - 0.6xfs hz passband ripple (0 - 0.4fs) - - 0.03 db stopband 0.6xfs - - hz stopband rejection 76 - - db group delay - - 18/fs s analog-to-digital converters (notes 1, 3) parameter min typ max units comment resolution - 16 - bits note 2 signal-to-noise line inputs - 85 - db mic inputs (mic gain = 0db) - 85 - db total harmonic distortion line - 0.02 - % mic - 0.02 - % HMP9701A
15 interchannel isolation line/line - 80 - db note 2 line/mic - 80 - db note 2 line/aux - 80 - db note 2 line/video - 80 - db note 2 gain error (full scale) - 5- % inter-channel gain mismatch - - 0.5 db offset error (0db gain) - 20 200 lsb gain drift - 100 - ppm/ o c note 2 analog-to-digital converters (notes 1, 3) (continued) parameter min typ max units comment digital-to-analog converters (notes 1, 4) parameter min typ max units comment resolution 16 17 - bits note 2 signal-to-noise - 87 - db total harmonic distortion - 0.02 - % interchannel isolation (line out) - 75 - db note 2 interchannel gain mismatch - 0.35 - db gain error - - 5 % note 6 gain drift - 100 ppm/ o c note 2 total out of band energy (28.8khz - 100khz) - - -50 db note 2 mute attenuation (0db) 80 - - db audible out of band energy (20khz - 28.8khz) - - -65 db note 2 deviation from linear phase - - 1 degree note 2 programmable attenuation/gain (note 1) parameter min typ max units record gain (0db to 22.5db) - 22.5 - db record gain step size - 1.5 0.2 - db pcm output volume span (+12db to -34.5db) - 46.5 - db pcm output volume span step size - 1.5 0.2 - db master volume span for line_out, mono_out (0db to -46.5db) - 46.5 - db master volume step size - 1.5 0.2 - db mixer input gain span for line_in, cd, video, aux, phone, mic (+12db to -34.5db) - 46.5 - db mixer input gain step size - 1.5 0.2 - db pc_beep attenuation span (0db to 45db) - 45 - db pc_beep attenuation step size - 3 0.2 - db HMP9701A
16 analog inputs (note 1) parameter min typ max units comment full scale input voltages mic inputs with 0db gain - 2.83 10% - v pp mic inputs with 0db gain - 1.0 - v rms mic inputs with 20db gain enabled - 0.283 10% - v pp mic inputs with 20db gain enabled - 0.1 - v rms line_in, cd, video, aux, and phone inputs - 2.83 10% - v pp line_in, cd, video, aux, and phone inputs - 1.0 - v rms input impedance 10 - - k w note 2 input capacitance - 15 - pf note 2 analog outputs (note 1) parameter min typ max units comment full scale output voltages line_out and mono_out - 2.83 10% - v pp line_out and mono_out - 1.0 - v rms external load impedance 10 - - k w external load capacitance - - 50 pf note 2 v ref output voltage - 2.25 10% - v v ref drive current - 5 - ma v ref output impedance - 4 - k w note 2 notes: 1. t a = 25 o c, v aa = v dd = 5.0v 2. guaranteed but not production tested. 3. based on 1khz, full scale analog tone input; measurement bandwidth is 20 to 20khz, a-weighted. 4. dacs driven with 1khz, full scale pcm sine wave, output measurement bandwidth is 20 to 20khz, a-weighted. 5. test performed with c l = 40pf, i ol = 4ma, i oh = -4ma. input reference level is 1.5v for all inputs. v ih = 3.0v, v il = 0v. 6. this is measured relative to a nominal output level. HMP9701A
17 adc/dac filter response curves figure 10. analog-to-digital frequency response (full scale line inputs, 0db) figure 11. analog-to-digital passband frequency response (full scale line inputs, 0db) figure 12. analog-to-digital transition band frequency response (full scale line inputs, 0db) figure 13. digital-to-analog frequency response (full scale inputs, 0db) figure 14. digital-to-analog passband frequency response (full scale inputs, 0db) figure 15. digital-to-analog transition band fre- quency response (full scale inputs, 0db) frequency (xf s ) magnitude (db) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0.00 0.06 0.13 0.19 0.25 0.31 0.38 0.44 0.50 0.56 0.63 0.69 0.75 0.81 0.88 0.94 1.00 frequency (xf s ) magnitude (db) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -0.2 0.00 0.03 0.06 0.08 0.11 0.14 0.17 0.20 0.23 0.25 0.28 0.31 0.34 0.37 0.40 0.42 frequency (xf s ) magnitude (db) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0.40 0.42 0.45 0.48 0.51 0.54 0.57 0.60 0.63 0.66 0.69 0.72 0.75 0.78 frequency (xf s ) magnitude (db) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0.00 0.07 0.13 0.19 0.25 0.32 0.38 0.44 0.50 0.57 0.63 0.69 0.75 0.82 0.88 0.94 frequency (xf s ) magnitude (db) 0.05 0 -0.05 -0.10 -0.15 -0.20 0.00 0.07 0.14 0.20 0.27 0.34 0.40 frequency (xf s ) magnitude (db) 0.40 0.46 0.53 0.60 0.66 0.73 0.80 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 HMP9701A
18 ac timing waveforms figure 16. cold reset timing figure 17. ate test mode figure 18. warm reset timing figure 19. rise and fall times figure 20. clocks figure 21. powerdown figure 22. digital setup and hold t crl t r2bc reset bit_clk t su2rst t hz hi-z reset sdata_out bit_clk, sdata_in t srh t s2bc sync bit_clk t rf t rf bit_clk, sdata_in 0.8v 2.0v t bch t bcl bit_clk t sh t sl sync slot 12 tag write to 26h data pr4 = 1 slot 12 tag note: bclk not to scale. slot 1 slot 2 t pdwn bit_clk sdata_in sdata_out dont care t su t hd sync bit_clk sdata_in sdata_out HMP9701A
19 typical application schematic diagram phone aux_l aux_r video_l video_r cd_l cd_gnd cd_r mic1 mic2 line_in_l line_in_r v aa agnd vref vref out afilt1 afilt2 afilt3 nc reserved nc line_out_l line_out_r v dd xtl_in xtl_out gnd sdata_out bit_clk gnd sdata_in v dd sync reset pc_beep nc nc nc nc nc nc agnd nc nc reserved v aa mono_out 1 m f 18pf (np0) 18pf (np0) 0.1 m f +5v analog power supply 1 m f 1.0 m f 0.1 m f mono out 48 47 46 45 44 43 42 41 40 39 38 37 HMP9701A 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 3 2 1 right line out left line out refernece voltage out pc_beep phone aux left aux right video left video right cd left cd ground cd right mic1 mic2 line_in left line_in right 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 1.0 m f 0.1 m f 0.1 m f 1nf (np0) 1 m f 1nf (np0) 1nf (np0) 0.1 m f 1 m f to 10 m f 0.1 m f ac_link interface 1 2 3 4 5 6 sd_out bit_clk sd_in sync reset to ac 97 compliant controller/interface ic + + + to 10 m f + analog gnd digital gnd 4 24.5760mhz (parallel) 0.1 m f +5v digital power supply HMP9701A HMP9701A
20 typical application schematic notes 1. a note about the capacitors used for coupling externally input audio or for outputting audio externally: the capacitance value and the associated circuit imped- ances will determine the lower frequency cutoff of the au- dio signal. the designer must determine what the circuit impedances are and select the coupling capacitor value accordingly. ceramic types (over electrolytic) are highly recommended. 2. the crystal should be a parallel resonant type, frequency is 24.756mhz, initial room temperature tolerance of 50ppm, and a load cap of about 16-20pf. 3. it is recommended to decouple each analog and digital power supply pin with a combination of a small value and large value bypass capacitor. the large value capacitor should be either a tantalum or aluminum electrolytic type. 4. locate all decoupling capacitors close to their associat- ed pins on the codec. 5. please note that all analog inputs and outputs of the HMP9701A codec are at the dc level of v ref and re- quire ac coupling to zero biased signal sources and destinations. 6. keep all analog input and output traces as short as possible, prevent any coupling from adjacent digital lines. 7. for optimum performance, it is preferred to layout sepa- rate analog and digital ground planes, joining them together at a point directly adjacent to the codec (i.e., di- rectly under it). this case is true even if the designer is using a single supply for the codec; the single supply should have adequate decoupling/isolation between the digital and analog sections. 8. when using an external clock source, please feed that signal into the xtl_in pin and leave the xtl_out pin unconnected. also, do not use any capacitors between xtl_in and gnd or xtl_out and gnd in that mode. HMP9701A

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